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MME U880 is an East German Z80 clone, which later after reunification of Germany was briefly produced and sold as Thesys Z80. U880 was also available as an export version - MME 80A-CPU, with 2.54” lead pitch. Also, Romanian Microelectronica Bucharest MMN 80CPU, and supposedly some of post-Soviet T34VM1 and K1518VM1 were using MME manufactured CPU dies. (I have two KR1858VM1 CPUs, dated 9305 and 9306, and they do not test as U880) MME U880 is highly compatible with the Zilog Z80 NMOS CPUs. There is a known difference in the CF flags behavior with OUTI instruction.
The OUTI instruction reads a byte from (HL) and writes it to the (C) port. HL is then incremented, and B is decremented. According to the Zilog Z80 documentation, page 309, this instruction does not affect CF flag. In practice, when the B value prior to executing OUTI is 1, (HL value prior to executing OUTI is 0FFFFh), most Z80 processors will clear the CF. U880 does not clear the CF in this case.
Sample test code:
MOV HL,0FFFFh
MOV BC,0100h
SCF
OUTI
JP C,U880
; Not a U880 CPU
Z80:
...
; A U880 CPU
U880:
...
It have been suggested that it is likely that soviet/post-soviet T34VM1 / KR1858VM1 CPUs were manufactured using either U880 dies or masks. Two KR1858VM1 CPUs, dated 9305 and 9306 do not pass the test above, and work more like the original Z80, which suggests an independent design or reverse engineering.
The behavior of the undocumented instruction with the op code 0EDh, 71h is different between most NMOS and CMOS Z80 processors.
Sample test code
MOV C,82h ; note - the port needs to be a read/write port, that can be read back
DB 0EDh, 071h ; undocumented OUT (C),<0|0FFH> instruction
IN A,(82h) ; read back the register
CP 0 ; is it zero?
JP Z,NMOS
; A CMOS CPU
CMOS:
...
; An NMOS CPU
NMOS
...
Z80 FLAGS register has two officially unused flag bits:
The behavior of these bits has been researched by many people and documented in several places online. Although, through my research I found that most of the documentation is either incomplete or incorrect. More specifically, on some CPU types in certain cases these flags are not set up deterministically and are possibly set to whatever a floating signal inside a processor reads at that moment.
Some people theorized that there is a hidden Q register, that keeps the result ALU operations. And for the ALU instructions, FLAGS.5 and FLAGS.3 bits will be set to the corresponding bits of that result, Q register. For example, OR 28h will set both bits, while AND 0D7h will clear both.
The things get more interesting for the instructions that do not produce an 8-bit result, particularly:
The effect SCF and CCF instructions on FLAGS.5 and FLAGS.3 bits is known to be different between different Z80 CPU types and manufacturers.
There seem to be several cases here:
All tested CPUs produce a consistent and reproducible result when SCF or CCF follow another instruction that sets FLAGS, excluding POP AF. In this case, the resulting flags seem simply to be a copy of the corresponding A register (accumulator) bits.
In the case were SCF or CCF is executed after an instruction that does not modify flags, for example POP AF, and both FLAGS.5 and A.5 or FLAGS.3 and A.3 are set or not set, the result seems to be a logic AND between the corresponding bits, that is: FLAGS.5 = FLAGS.5 & A.5 FLAGS.3 = FLAGS.3 & A.3
Behavior in this case depends on the CPU type. Here is the list of known/tested CPUs and their corresponding behaviors:
Behavior in this case depends on the CPU type. Here is the list of known/tested CPUs and their corresponding behaviors:
BIT n,(HL) sets YF and XF to what appear to be bits 13 and 11 of an internal register that is typically refereced as MEMPTR. The value of MEMPTR is typically modified by the instructions that use 16-bit values, for example: LD A,(rp); JP, ADD rp1,rp2; OUT (C),A, etc.
Supposedly the behavior of KR1858VM1 for LD (rp),A and OUT (port),A differs from that of other Z80 CPUs, but in my tests I wasn’t able to find any differences.