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Xi 8088 CPLD

Introduction


This is a "work in progress" page for my Xi 8088 CPLD project. It is in the concept / requirements collection stage now, and it is not clear if I am actually going to build this project.

Project goals

  • Build a small (about 6.5"x4") 8088/V20 CPU board with ISA interface
  • Use CPLD instead of discrete logic
  • Optional: Use SMT components (easy to solder - 0805 discretes, SOIC and PLCC IC packages)

TODO List

  • Reverse X-Bus 74F245 transceivers, so that 'B' side is connected to ISA.
  • Connect memory data bus to X-Bus
  • Rewrite CPLD pin allocation as a table (pin type / signal name / pin number)
  • Review SMT resistor array options
  • Work on initial PCB layout, determine size of the PCB.

Technical Details

Design Ideas

  • Atmel ATF1508AS CPLD with JTAG interface
    • Clock generation:
      • 8284 implementation
      • 50% duty cycle 4.77 MHz DMA clock
      • 1.19 MHz PIT clock
      • 7.16 MHz KBC clock
      • Glitchless turbo switching
      • Programmable selection of 33% or 50% duty cycle for turbo CPU clock
    • Wait state generator:
      • Programmable number of I/O wait states (0 to 4)
      • /0WS support (no wait states for fast ISA devices)
      • Possibly programmable selection of wait states per device (pending CPLD cells availability)
    • Bus arbitration logic
    • I/O chip select logic
      • PIC#1, PIC#2, PIT, DMA, KBC, RTC
    • Memory chip select logic
      • Programmable UMB configuration (map to SRAM) in 32KiB blocks
      • Programmable Flash ROM configuration - in 32KiB or 64 KiB blocks
      • Option: automatically disable UMB for areas that are mapped to Flash ROM (pending CPLD cells availability)
    • DMA page register
      • 74LS670 like, only 3 registers?
    • Port B logic
      • I/O check NMI generation
      • PIT/Speaker control
    • XDIR logic
  • CPLD Pin allocation
    • Total: 64 I/O pins in JTAG mode
    • Output: 27 pins
    • Input: 25 pins
    • Bidirectional: 12 pins
  • Chipset control
    • Two registers: index and data
      • clock / wait cycle control - 1 reg
      • RAM CS - 1 reg
      • ROM CS - 1 reg
      • Version- 1 reg
    • Implement a programmable clock divider for turbo mode, to get 50% (for V20) or 33% (for 8088) duty ratio.
      • 1 bit (divide by 2 / divide by 3) - always divide by 3 if in non-turbo mode
    • Implement programmable I/O wait cycles
      • From 0 to 4 wait states (3 bits?!) combine with above?
    • Implement programmable /RAM2_CS (enabled/disabled using 32KiB blocks)
      • C0000, C8000, D0000, D8000, E0000, E8000, F0000, F8000 - 8 bits
    • Implement programmable /ROM_CS
      • C0000, C8000, D0000, D80000, E0000, E8000, F0000, F8000 - 8 bits, combine with above, or add support for bigger (256KiB flash)?
    • Implement a version register (hardwired)?
      • 4 bits - major version
      • 4 bits - minor version
  • Build a CPLD test board first:
    • PLCC84 SMT socket
    • Two half can oscillator sockets (connect to global clock?!)
    • One 14 pin DIP socket for 74F14 (or just some prototype space)
    • Switch (for reset), reset circuit, decoupling capacitors
    • Turbo switch jumper
    • Turbo LED
    • 5x2 pin JTAG header
    • Two 17x2 pin headers for I/O connections
    • Power connector
  • Testing:
    1. Test 8284 / clock generator circuit
    2. Test chip select logic (memory, I/O)
    3. Test Bus Arbitration and Wait Logic (BAL)

Component Selection

  • 8088/V20 CPU and 8087 FPU in DIP40 packages.
  • 8288 bus controller in DIP20 package. That is the only available package for this part.
  • Crystal oscillators in "half can" DIP packages. This is to simplify testing different CPUs at different frequencies.
  • 82C59,82C54,82C42,82C37 in PLCC28/PLCC44 packages. SMT PLCC sockets to be used, at least for the first (test) board.
  • AS6C4008 SRAM in SOIC package.
  • ST39C010 Flash ROM in PLCC32 package.
  • ATF1508AS CPLD in PLCC84 package
  • 74F573, 74F245, 74F244, 74F14, 74F06 in SOIC packages. It is an SMT package with relatively large pitch (1.27 mm).
  • Discrete components (resistors and capacitors) in 0805 SMT packages (2x1.27mm).
  • Through hole jumpers, connectors, switch, and LEDs.
  • Decide on resistor arrays - SMT or through hole?

CPLD Pin Allocation

Assumptions

  • A15 is used as /RAM1_CS - chip select for the first SRAM (00000h-7FFFFh)
  • Number of I/O pins on ATF1508AS CPLD with JTAG enabled
    • Total: 64
    • Special signals:
      • Reset: 1
      • Clock inputs : 2
      • Output enable?!

Clock and Reset Logic

  • RES_IN - reset circuit output - CPLD input, clock generation, Port 61h, wait logic
  • OSC - 14.31818 MHz oscillator output - CPLD clock input, clock generation
  • TURBO_OSC - 24 MHz - 32 MHz oscillator output - CPLD clock input, clock generation
  • TURBO_SW - turbo switch - CPLD input, clock generation
  • TURBO_LED - turbo on LED - CPLD output (optional)
  • CLK88 - CPU clock to 8088, 8087, and 8288 - CPLD output, clock generation
  • READY - Ready signal to 8088 and 8087 - CPLD output, clock generation
  • RESET - Reset signal to 8088 and 8087 - CPLD output, clock generation
  • DMACLK - DMA clock - CPLD output, clock generation
  • OSC/12 - PIT clock input - CPLD output, clock generation
  • OSC/2 - Keyboard clock - CPLD output, clock generation
  • Total: 11(10)

X-Bus - Address, Data, and Control Signals

  • XD0-XD7 - Data bus - CPLD input/output/tristate - Port 61h read/write, DMA Page write, CPLD (system) configuration registers?
  • XA0,XA4-XA7,A8-A9 - Address bus - CPLD input - on-board I/O chip select logic
  • A15 - Address bus -  CPLD input - memory chip select for UMB (optional)
  • A16-A19 - Address bus - CPLD input/output/tristate - Memory chip select, DMA page output
  • /XIOR, /XIOW, /XMEMR - I/O read, I/O write, memory read - CPLD input, bus arbitration, wait logic, Port 61h, RTC, XDIR signal
  • /INTA - Interrupt acknowledge from 8088 - CPLD input, XDIR signal
  • XDIR - XD0-XD7 transceiver direction - CPLD output, XDIR signal
  • Total: 25(24)

Bus Arbitration and Wait Logic

  • /S0, /S1, /LOCK - Status signals from 8088 - CPLD input, bus arbitration
  • IOREADY (IOCHRDY) - Wait signal fro ISA bus - CPLD input, wait logic
  • AENBRD - CPU bus disconnect - CPLD output, bus arbitration
  • /DMAAEN - DMA address enable to /XIOR,/XIOW,/XMEMR,/XMEMW and XA0-XA7 transceivers  - CPLD output, bus arbitration
  • RDYTODMA - ready signal to DMA - CPLD output, bus arbitration, wait logic
  • HRQDMA - hold request from DMA - CPLD input, bus arbitration
  • HOLDA - hold acknowledge to DMA - CPLD output, bus arbitration
  • Total: 9

Port B (61h), NMI Logic, and Speaker

  • NMI - Non-maskable interrupt to 8088 - CPLD output, NMI logic, Port 61h
  • /IOCHK - Non-maskable interrupt output from ISA - CPLD input, NMI logic, Port 61h
  • GATE2 - timer #2 gate input - CPLD output, Port 61h
  • OUT1, OUT2 - timer #1 and timer #2 outputs - CPLD input, Port 61h
  • SPEAKER - speaker - CPLD output, Port 61h
  • Total: 6

DMA Page Register

  • /DACK2, /DACK3 - DMA Page register address - CPLD input, DMA page
  • Total: 2

I/O Chip Select

  • /DMA_CS - DMA chip select - CPLD output, on-board I/O chip select logic
  • /PIC1_CS, /PIC2_CS - PIC chip select - CPLD output, on-board I/O chip select logic
  • /PIT_CS - PIT chip select - CPLD output, on-board I/O chip select logic
  • /KEY_CS - Keyboard controller chip select - CPLD output, on-board I/O chip select logic
  • RTC_ALE, /RTCR, /RTCW - RTC select, read, write signals - CPLD output, on-board I/O chip select logic
  • Total: 8
Memory Chip Select
  • /RAM2_CS - chip select for the second SRAM (80000h-9FFFFh, UMB)- CPLD output, memory chip select
  • /ROM_CS - chip select for the Flash ROM - CPLD output, memory chip select
  • Total: 2

Buffered and Inverted Signals

  • OSCDRV buffered OSC - 14.31818 MHz oscillator output, ISA input
  • CLK - buffered CLK88 - CPLD output, ISA input
  • RESETDRV - buffered RESET - CPLD output, ISA input
  • /AEN - inverted AENBRD - CPLD output, 8288 input
  • /DEN - inverted DEN - 8288 output, AD[0-7] to D[0-7] transceiver enable
  • TC - inverted /TC - 8237 output, ISA input



 # Input signal
 Pin#
 Description
 Output signal Pin#
 Description Bi-dir signal
 Pin#
 Description
 1 RES  Reset from Schmitt trigger
 RESET  global reset, CPU, peripherals, ISA XD0  DMA page (I), Port 61h (I/O), Chipset control (I/O?)
 2 OSC  14.31818 MHz from oscillator CLK88   to CPU and to ISA XD1   DMA page (I), Port 61h (I/O), Chipset control (I/O?)
 3 TURBO_OSC  24-40 MHz from oscillator READY  to CPU XD2
  DMA page (I), Port 61h (I/O), Chipset control (I/O?)
 4 /S0  from CPU CLK_KBC  7.16 MHz to KBC XD3   DMA page (I), Port 61h (I/O), Chipset control (I/O?)
 5 /S1  from CPU CLK_DMA  4.77 MHz to DMAC XD4   Port 61h (O), Chipset control (I/O?)
 6 /LOCK  from CPU CLK_PIT  1.19 MHz to PIT XD5   Port 61h (O), Chipset control (I/O?)
 7 TURBO_SW
  enable turbo, from turbo switch TURBO_LED  Turbo LED XD6
  Port 61h (O), Chipset control (I/O?)
 8 HRQDMA  from DMAC READYTODMA  to DMAC XD7   Port 61h (O), NMI Register (O), Chipset control (I/O?)
 9 /XIOR   AENBRD   A16   DMA page (O), Memory CS (I)
 10 /XIOW   /DMAAEN   A17   DMA page (O), Memory CS (I)
 11 /INTA  from 8288 HOLDA  to DMAC A18   DMA page (O), Memory CS (I)
 12 IOREADY  from ISA XDIR  or /XDIR A19
  DMA page (O), Memory CS (I)
 13 /OWS  from ISA NMI  to CPU   
 14 /IOCHK   from ISA PIT_GATE2  to PIT   
 15 /DACK2  from DMAC SPEAKER     
 16 /DACK3  from DMAC /DMA_CS     
 17 PIT_OUT1  from PIT /PIC1_CS     
 18 PIT_OUT2  from PIT /PIT_CS     
 19 XA0   /PIC2_CS     
 20 XA1   /KBC_CS     
 21 XA4   RTC_ALE     
 22 XA5   /RTCW     
 23 XA6   /RTCR     
 24 XA7   /ROM_CS     
 25 A8   /RAM2_CS     
 26 A9        
 27 A15        

Bill of Materials

 Component Type
 Reference Description Quantity Possible Sources and Notes
 PCB  Xi 8088 CPLD PCB
 1 Order from OSH Park
 Mounting Bracket
  Keystone 9205
 1 Mouser (+)
 Screw  Screw 4-40 diameter, 1/4" lenght
 2 Mouser (+)
 Battery Holder
 BT1 CR2032 batter holder, 20 mm lead spacing 1 Mouser (+)
 Capacitor C1 - C29
 0.1 uF, 0805 SMT
 29 Mouser CGJ4J2X7R1H104K (-)
 Capacitor C30 - C35
 10 uF, 0805 SMT
 5 Mouser CGA4J1X7R0J106K (-)
 Capacitor C36 0.01 uF, 0805 SMT
 1 Mouser C2012X7R2A103M (-)
 Capacitor C37 - C40
 47 pf, 0805 SMT
 4 Mouser VJ0805A470GXQPW1BC (-)
 Diode D1 1N4148, SMT
 1 Mouser (-)
 LED Indicator
 D2, D3
 Bi-level LED indicator  1 Mouser (+)
 Fuse F1 1.1A, SMT
 1 Mouser (-)
 Connector J1, J2, P3, P4, P5  12x1 pin header  1 Mouser (-)
 Connector J3 3x1 pin header
 1 Mouser (+)
 Connector J4 6x2 pin header
 1 Mouser (+)
 Connector J5, J6
 2x1 pin header
 2 Mouser (+)
 Connector P1, P2
 6 pin Mini-DIN connector (Purple, Green) 2 Mouser (+)
 Resistor R1 100 kOhm, 0805 SMT
 1 Mouser (-)
 Resistor R2, R4, R5
 470 Ohm, 0805 SMT
 3 Mouser (-), Can use a resistor array for R4 and R5?
 Resistor R3 10 k0hm, 0805 SMT
 1 Mouser (-), Use a pull up from a resistor array instead?
 Resistor R6 1 k, 0805 SMT
 1 Mouser (-)
 Resistor
 R7 33 Ohm, 0805 SMT
 1 Mouser (-)
 Resistor Array
 RR1 - RR3
 10 kOhm x 9
 3 Mouser (-)
 Resistor Array
 RR5 10 kOhm x 5
 1 Mouser (-)
 Resistor Array
 RR6 470 Ohm x 5
 1 Mouser (-)
 Speaker SP1 12 mm speaker 1 Mouser (-)
 Switch SW1 6 mm tactile switch, right angle
 1 Mouser (+)
 IC U1 ATF1508AS 1 Mouser (+)
 IC U2 8088, 80C88, V20, V20HL
 1 Utsource (+)
 IC U3 8087-1 1 Utsource (+)
 IC U4 CP82C88Z 1 Avnet (o)
 IC U5, U6
 CS82C59 2 Avnet (+)
 IC U7 CS82C37 1 Intersil (+)
 IC U8 CS82C54 1 Avnet (+)
 IC U9 VT82C42V 1 Utsource (o)
 IC U10 DS12885, SOIC
 1 Maxim (+)
 IC U11, U12
 AS6C4008, SOIC
 2 Mouser (-)
 IC U13 ST39SF010, PLCC32
 1 Avnet (+)
 IC U14 - U16
 74F573, SOIC20
 3 Avnet (+)
 IC U17 - U20
 74F245, SOIC20
 4 Avnet (+)
 IC U21 74F244, SOIC20
 1 Avnet (+)
 IC U22 74F14 or 74AHCT14, SOIC14
 1 Mouser (-)
 IC U23 74LS06, SOIC14
 1 Avnet (+)
 Crystal Oscillator U24 14.31818 MHz, half can, DIP
 1 Mouser (-)
 Crystal Oscillator
 U25 24 MHz - 32 MHz, half can, DIP
 1 Mouser (-, 24 MHz, 30 MHz, 32 MHz, 40 MHz)
 IC Socket U1 84 pin PLCC, SMT 1 Avnet 8484-21A1-RK-TP (+)
 IC Socket
 U2, U3
 40 pin 600 mil DIP socket  2 Mouser 40-6518-10 (+)
 IC Socket
 U4 20 pin 300 mil DIP socket  1 Mouser 20-3518-10 (+)
 IC Socket
 U5, U6, U8
 28 pin PLCC, SMT
 3 Mouser 8428-21A1-RK-TP (-)
 IC Socket
 U7, U9
 44 pin PLCC, SMT
 2 Avnet 8444-21A1-RK-TP (+)
 IC Socket
 U13 32 pin PLCC, SMT
 1 Avnet 8432-21A1-RK-TP (+)
 Oscillator Socket
 U24, U25
4 pin 300 mil DIP half can oscillator socket  2 Mouser 535-1108800 (-)

Ċ
8088-SBC-CPLD - Schematic - BW - 1.0b2.pdf
(314k)
Sergey Kiselev,
Oct 9, 2012, 12:38 AM
v.1
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