Home‎ > ‎Sergey's Projects‎ > ‎Sergey's XT‎ > ‎

Historical Notes

This page contains random historical facts about Intel 8000 family and IBM PC computers that I've discovered while building my system.

Intel 80C88 processor?

"CMOS version of 8086 features operating current of 10mA/MHz maximum" article from IEEE Micro (October 1983) magazine mentions that Harris Semiconductor had developed the CMOS version of 80C86 (and so I assume 80C88) and that both Harris and Intel will manufacture CMOS 80C86 CPUs using Harris design. Now here is the puzzle: Intel 80C88 behaves differently (see "Disabling interrupts after PUSH sreg") from Harris 80C88, so it appears that Intel CPUs were made using a different design. Moreover all Intel 80C88 I've seen so far marked as "Made in Japan" and as far as I know Intel never had manufacturing facilities in Japan. But here is the possible solution: The packages of Intel 80C88 and other 82Cxx support ICs look extremely similar to these of OKI, so I assume that OKI made them for Intel.

8237 DMA Controller

When working on DMA implementation I was wondering why it is so difficult to interface 8237 controller to a 8088 system. 8237 supports only 16-bit address (8088 has 20-bit address bus) so it requires a separate page register for providing missing 4-bits of address.  A special bus arbitration logic is needed when using 8088 maximum mode. The clock requirements of the DMA chip are different from these of CPU - CPU uses 33% duty cycle clock and DMA requires 50% duty cycle.
So the answer is that 8237 was not designed for 8088 CPUs (which is odd given that Intel released this chip in 1979, when 8086 and 8088 already existed).
In fact 8237 was designed by AMD. The AMD part number is Am9517A (the AMD datasheet contains following note "The 8237A is an AMD-invented device more commonly referred to as the Am9517A"). There is an anouncement in InfoWorld magazine (May 9, 1979) saying that Intel introduced 8237 (3 MHz) and 8237-2 (5 MHz) DMA controllers that are pin equivalent of AMD 9517. It says nothing though about using AMD's design by Intel, but it was the case. In fact on Intel 8237 chips there is an AMD copyright marking. I guess that Intel received 8237 design from AMD as a part of portfolio exchange (perhaps the same exchange that allowed AMD to manufacture 8086 and 8088 processors).

Intel had a better alternative for 8237 - Intel 8089 I/O coprocessor. The 8089 is much more advanced than 8237 - it has its own instruction set and basically it is possible to program it to perform advanced I/O operations independently from CPU. But for whatever reason (perhaps the cost - the price for 8089 was about $80 and for 8237 - about $20, maybe availability, or maybe existing 8237 knowledge and experience) IBM decided not to use 8089 in IBM PC, and here we are stuck with inefficient and slow 8237 :-)

Errata and Undocumented Features in 8088 Processors

Stack change race condition


A logical address on x86 consists of two parts: 16-bit segment and 16-bit offset. In case of stack SS:SP registers pair is used. It is usually required to change both registers to move the stack to a new location. This usually done using following instructions sequence:
MOV SS,reg/mem
MOV SP,reg/imm/mem

Note that the stack location is not defined correctly between these two instructions. So if an interrupt occurs during that time a random memory locations (new SS, old SP, and below) will be modified, possibly corrupting program's or system's memory. Disabling interrupts using CLI before changing stack address does not provide complete workaround, because it doesn't disable NMI. Newer 8088 processors (Intel 8088 marked '81 or '81, '83, all CMOS 80C88, and all V20) don't check for interrupts after the MOV sreg,reg/mem and POP sreg instructions, effectively disabling the interrupts for one instruction. Note that interrupts are disabled after changing any segment register, not just SS (some sources mention that on 286+ processors interrupts are disabled only after changing SS). Early Intel 8088 processors (marked "INTEL '78" or "(C) 1978" on the package) don't provide this workaround, and therefore they are susceptible to memory corruption during stack location change.

Detection and workaround

Following technique could be used to detect CPUs with this issue:
1. Put CPU in single step mode
2. Execute an instruction that changes a segment register (DS or ES, do not use SS!)
3. Check if single step interrupt executed for address following the segment change instruction. If it is executed - the processor is buggy.
See cpu.inc file from Sergey's XT BIOS for the implementation.

(Partial) workaround is disabling interrupts before changing stack register. On IBM PC compatible computers it is also possible to disable NMIs (using port B - 61h).

Disabling interrupts after PUSH sreg


It is not a bug, but rather a strange behavior I noticed in Harris 80C88 processors (possibly also present in Intersil 80C88). These processors disable interrupts for the instruction following PUSH sreg instruction. It somehow resembles the fix for the previous issue (see "Stack change race condition"). Intel 80C88 processor in this case behaves normally and do not disable interrupt.

Detection and workaround

This behavior could be detected using the method described in the previous issue.
Not a bug - no workaround necessary

Segment override and REP prefix


All 8088 and 80C88 CPUs will not resume execution of string operation instructions prefixed by REP prefix and a segment override prefix, for example REP ES MOVSW. Some sources incorrectly indicate that the issue was fixed in 80C88 but my tests show that this issue present in Intel 80C88 and Harris 80C88 CPUs. Issue doesn't present in V20 CPUs, and it could be used to distinguish between 8088 and V20 (although there is an easier way - using AAD instruction. See below.).

Detection and workaround

Issue present in all 8088 and 80C88 CPUs. Following code could be used for workaround:
JCXZ done
JMP resume

POP CS instruction

All 8088 and 80C88 will execute POP CS instruction (0Fh), loading CS from the stack, and incrementing IP by 1.

FDC - NEC design